This invention relates to a converter for effecting a potential level conversion, and in particular to a converter whose output terminal can take a first level state, second level state and high impedance output state.
There is a demand for a converter for converting a logic level (for example, H=+10V, L=0V) of a CMOS (complementary MOS) to a logic level (for example, H=+5V, L=0V) of a DTL (diode transistor logic) or a TTL (transistor transistor logic). In this case, it is preferable that the converter can take a HIGH output (H=+5V) state, LOW output (L=0V) state and high impedance output state. When the output of the converter is shifted from low level (L=0) to high level (H=+5V), a sharp rise of a signal on the output terminal of the converter is particularly required. Where such a converter is constituted using IG-FET's (insulated gate field effect transistors), the IG-FET is connected between a potential supply terminal for supplying a TTL level of, for example, +5V and an output terminal. Where, however, a converter is constituted using an integrated circuit, a potential level (for example, +10V) equal to a CMOS logic level is applied to a substrate of the IG-FET. In consequence, the threshold voltage of the IG-FET varies dependent upon a back gate bias effect, and a rise or fall (hereinafter referred to merely as a "rise") of the leading edge of the converter output is affected.
For ease in understanding the nature of this invention a converter circuit constituting part of this invention will be explained by referring to FIG. 1.
In FIG. 1, an input signal 1N(H=10V, L=0V) from an input terminal 1 is supplied to one input of a NAND gate 2 and NOR gate 3. A control signal EN(H=+10V, L=0V) is supplied to the other input of NAND gate 2 and a negation signal EN is supplied to the other input of NOR gate 3. A first IG-FET 6 of P-channel type is arranged together with a second IG-FET 7 of an N-channel type. The output of NAND gate 2 is supplied to the gate of the first IG-FET 6 and the output of NAND gate 3 is supplied to the gate of the second IG-FET 7. The source of the first IG-FET 6 is connected to a supply terminal 8 of a first potential V.sub.CC (for example, +5v) and the drain of the first IG-FET 6 is connected to an output terminal 9. The source of IG-FET 7 is connected to a second potential (for example, 0V) supply terminal E, and the drain of IG-FET 7 is connected to the output terminal 9. The substrate electrode of IG-FET 6 is connected to a supply terminal 10 for supplying a third potential V.sub.DD (+10V), and the substrate electrode of IG-FET 7 is connected to the second potential supply terminal E. For example, NAND gate 2 is shown in FIG. 2 and NOR gate 3 is shown in FIG. 3.
In FIG. 1, when EN=0V, the output of NAND gate 2 is +10V and the output of NOR gate 3 is 0V. Thus, IG-FET's 6 and 7 are rendered OFF and the output terminal 9 becomes a high impedance state. When EN=+10V and IN=+10V, the output of NAND gate 2 is 0V and the output of NOR gate 3 is 0V. Thus, IG-FET 6 is rendered ON and IG-FET 7 is rendered OFF. As a result, the output terminal 9 becomes a +5V output state. Stated in another way, the level +10V of the input signal IN is converted to a level of +5V. When IN=0V at EN=+10V, the output of NAND gate 2 becomes +10V and the output of NAND gate 3 becomes +10v. Thus, IG-FET 6 is rendered OFF and IG-FET 7 is rendered ON. In consequence, the output terminal 9 becomes a "0V" output state.
As set out above, a voltage (10V) higher than the source potential (+5V) is applied to the substrate electrode of IG-FET 6. In consequence, IG-FET 6 is in the so-called "back gate bias" state. Since the threshold voltage of IG-FET 6 is increased i.e. the gate-to-source voltage is decreased, the output current of IG-FET 6 is decreased. For this reason, a rise time of the output voltage is lengthened when a potential on the output terminal 9 is shifted from 0V to +5V.
It is accordingly the object of this invention to provide a converter capable of producing three output states, which converter includes a compensation circuit which permits a rise of the leading edge of the converter output to be sharpened.